1. Field of the Invention
The present invention generally relates to delay buffers, and more particularly to a delay buffer circuit using gated driver tree architecture.
2. The Prior Arts
In recent years, as wireless networks are gaining widespread popularity, numerous communications standards are established and adopted, mobile communications devices such as handsets, personal digital assistants (PDA), etc., have become the mainstream product of consumer electronics market. Most of the mobile communications devices are powered by a battery and, as these devices are getting increasingly complicated and functional-rich, how to let batteries of a limited capacity to sustain these devices for the longest operation time concerns all product vendors. One of the approaches is of course to reduce the power consumption of these devices' relevant circuits.
In a digital processing chip of mobile communications, the delay buffer takes up a large portion of the circuit layout. If the power consumption of the delay buffer could be reduced significantly, the overall power consumption of the digital processing chip could be reduced significantly as well. On the other hand, as these chips are working at even higher operation frequencies, a new, low-power delay buffer should be operable under high frequencies. FIG. 1 is a schematic diagram showing a conventional delay buffer having a length N and a data width W bits using shift registers. As illustrated, the delay buffer contains N×W shift registers 10, arranged between the input and the output in N stages, each with W shift registers. The N×W shift registers are triggered by a same clock signal CLK. For every clock period of CLK, W-bit data is shifted from W shift registers of a previous stage to those of a next stage, and so on. A W-bit data input N clock periods ago therefore would be delayed and output after N clock periods. The clock signal CLK is provided to all N×W shift registers, contributing to the high power consumption. Moreover, the N×W shift registers would also take up a large die area. Therefore, in real life, delay buffer such as the one in FIG. 1 is seldom used.
One of the common delay buffer implementation is a dual-port SRAM memory whose operation is different from that of the shift-register-based delay buffer. For an N×W SRAM-based delay buffer, there is no data movement between stages. Instead, at every clock period, a W-bit data is written to one of the N×W storage locations of the SRAM-based delay buffer, and another W-bit data that is written N clock periods ago is output. The power consumption of a SRAM-based delay buffer is mainly from the address decoder and the drivers for its input and output ports. As memory related technology has already quite mature and satisfactory results in terms of layout area and speed are achievable. Therefore in reality a delay buffer is often implemented using SRAM memory.